A typical continuous time delta sigma analog-to-digital converter includes a loop filter, a clocked quantizer and one or more feedback digital-to-analog (DAC) converters. Ideally, when the quantizer is toggled, the feedback DACs should output a signal instantaneously. In practice, this is not possible due to finite switching times which introduce an unavoidable delay in the quantizer and the feedback DACs. This effect is known as excess loop delay. To compensate for this, a direct feedback path from the output may be input to a node between the loop filter and the quantizer. Examples of continuous time delta sigma converters are disclosed in U.S. Pat. No. 7,405,687 and U.S. Patent Publ. No. 2007/0171109, which are herein incorporated by reference.
When a multiphase voltage controlled oscillator (VCO) is used as a quantizer and integrator, the excess loop delay becomes even more problematic because a VCO based quantizer will also integrate its input signal.
Another problem is the need for summation of multiple signals originating from one more integrators in the loop filter or feedback paths from the quantizer. A conventional prior active summing circuit may include a resistive summation amplifier, having one or more resistive inputs in conjunction with current steering DACs. The bandwidth of this arrangement is ideally given by the feedback factor, which is set by the ratio of the feedback, and total input and feedback resistances, multiplied by the unity gain-bandwidth of the amplifier.
Another prior passive summing circuit has current from the feedback DACs generate a voltage when passing thru resistances such as the equivalent resistance Req seen at the input node of the VCO due to one or possibly multiple resistive paths from the loop filter, realizing a summing point.
Common for both prior summing solutions is that the feedback coefficients are realized by IDAC*R, where R would be the amplifier feedback resistance or the equivalent resistance Req. While the latter approach has the potential for high power effectiveness, it has the disadvantage that parasitic capacitance associated with the input of the VCO, routing and DAC current sources form a pole in conjunction with the equivalent summing resistance.
An equivalent situation may arise with the former approach when a pole is formed at the inputs of the amplifier due to the parasitic capacitance associated with this node. In addition, the amplifier itself has a pole due to its finite bandwidth. Careful layout and optimization of the amplifiers' input capacitance maximizes the bandwidth. Nevertheless, to achieve wide bandwidth, the value of the resistors in the amplifier feedback network is preferably set low. However, this increases the power consumption and the small input resistors will also reduce the gain in the preceding integrators.
Another concern with the two previous summing solutions is with the current steering feedback DACs. The digital bits, which may have unitary coding, should arrive before the controlling edge of the clock signal. This is because a flip-flop or latch is used with each current cell. The setup-time of the logic is dependent on the type of logic used. If the setup time is violated because one of the current cells changes its output at a different point in time than the other current cells, noise degradation occurs in the continuous time delta sigma modulator.
Another concern for a continuous time delta sigma modulator is the delay from when the controlling edge of a clock signal arrives to a cell to when the updated current cells provides an output. At high operating frequencies relative to the maximum transistor switching speed, delay from a single logic block can be significant with respect to the sampling period, and if the logic block a part of the modulator feedback loop, the excess loop delay is increased. In conjunction with the parasitic poles from the aforementioned solutions, this also jeopardizes the stability of the modulator.